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E2C0022-27-Y3 Semiconductor
Semiconductor MSC1215-XX
This version: Nov. 1997 MSC1215-XX Previous version: Jul. 1996
17 2 Duplex Driver with Dimming, Keyscan and A/D Converter Function
GENERAL DESCRIPTION
The MSC1215-XX is a 1/2-duty vacuum fluorescent display tube driver implemented in BiCMOS technology. This LSI consists of a 37-bit shift register, 34 latches, an analog dimming circuit, (a PWM conversion circuit), a 34 keyscan circuit, a 6ch-6-bit A/D converter and 17 segment drivers, and 2-grid pre-drivers. The MSC1215-XX has capabilities of displaying audio system frequencies and various informations on a VFD tube for the automobile application and also interfacing with keyboard inputs and on an analog volume input. For automobile audio systems, the front panel functions (such as a frequency display, keyboard input and analog voltage input from a volume) can be accomplished by this IC. The analog dimming/PWM conversion modes can be selected automatically for the brightness control, so this IC is applicable to any type of automobile without any change of the specifications. The interface with a MCU can be done only with 3 wires (CS, DATA I/O and CLOCK signals). Also, DATA I/O and CLOCK signal lines can be shared with other peripherals because of chip select function by CS signal.
FEATURES
* Power supply voltage : VDD=8 to 18 V * Operating temperature range : Ta=-40 to +85C) * 17-segment driver outputs (IOH=-5mA at VOH=VDD-0.8 V) * Built-in analog dimming circuit (6-bit resolution, user-programmable) * Built-in PWM conversion circuit (Lamp PWM signal to vacuum fluorescent display PWM signal) * Built-in automatic-selection circuit for analog dimming/PWM conversion function * Built-in 6ch 6-bit A/D converter * Built-in 3 4 Keyscan circuit * Built-in oscillation circuit (external R and C, fOSC=3.3 MHz) * Built-in Power-On-Reset circuit * Package: 42-pin plastic DIP (DIP 42-P-600-2.54) (Product name: MSM1215-xxRS) xx indicates the code number.
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Semiconductor
MSC1215-XX
BLOCK DIAGRAM
SEG1 VDD P. O. R GND Regulator 5V 34AE17 Segment Control PWMOUT CS DATA I/O CLOCK SW1 OSC0 OSC1 VK VD D/A
Decoder De-glitch PWM detector Look up table 6-bit dig. comp. bit 34-18 (Grid2) bit 17-1 (Grid1) 3-bit Latch
SEG17
17 Segment VF Tube Driver
Test
Test1-8
SW1 (VF Data) SW2 (Keyscan) SW3 (A/D)
Timing
L
34-bit Latch
bit1 D bit34 34-bit Shift Register R
Mode Select
3-bit S/R
OSC
Timing Generator
Grid Pre-driver
GRID1 GRID2 to PWM OUT
+ -
MUX
Latch Select
PWM
Logarithm Counter
SI SW2
12-bit Presetable S/R Set S S 4 4 L 4 L 4 4
out PE
SW3
CH1 CH2 CH3 CH4 CH5 CH6
"H" at SW3 ON Read Eable Channel Select
Timing Generator
4-bit L Latch 4
VREF VREF
+ PE 36-bit S/R O
Read Enable "H"at SW2 ON
Timing Generator
Detector
6ch 6-bit A/D & Logic
Row 3 2 1 Col 4 3 2 1 With 100kW pull-up resistor
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MSC1215-XX
INPUT AND OUTPUT CONFIGURATION
* Schematic Diagrams of Logic Portion Input Circuit 1
VDD (5V Reg.)
INPUT
GND
GND
* Schematic Diagrams of Logic Portion Input * Schematic Diagrams of Logic Portion Input/ Circuit 2 Output Circuit
VDD (5V Reg.)
(5V Reg.)
VDD
(5V Reg.)
COLn
DATAI/O
GND
GND
GND
GND
GND
GND
* Schematic Diagrams of Logic Portion Output * Schematic Diagrams of Driver Output Circuit Circuit
(5V Reg.) (5V Reg.) VDD VDD
OUTPUT
OUTPUT
GND
GND
GND
GND
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PIN CONFIGURATION (TOP VIEW)
COL4 1 GRID1 2 GRID2 3 SEG 1 4 SEG 2 5 SEG 3 6 SEG 4 7 SEG 5 8 SEG 9 9 SEG10 10 SEG11 11 VDD 12 SEG12 13 SEG13 14 SEG14 15 SEG15 16 SEG16 17 SEG17 18 SEG 6 19 SEG 7 20 SEG 8 21
42 COL3 41 COL2 40 COL1 39 VD 38 VREF 37 CH6 36 CH5 35 CH4 34 CH3 33 CH2 32 CH1 31 GND 30 OSC0 29 OSC1 28 VK 27 DATA I/O 26 CS 25 CLOCK 24 ROW 1 23 ROW 2 22 ROW 3
42-Pin Plastic DIP
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage (1) Input Voltage (2) Power Dissipation Storage Temperature Symbol VDD VIN1 VIN2 PD TSTG Condition -- All inputs except VK VK Ta=85C -- Rating -0.3 to +20 -0.3 to +6 -0.3 to +VDD 400 -55 to +150 Unit V V V mW C
RECOMMENDED OPERATING CONDITION
Parameter Supply Voltage Operating Temperature High Level Input Voltage (1) High Level Input Voltage (2) Low Level Input Voltage Clock Frequency OSC Frequency Frame Frequency Symbol VDD TOP VIH1 VIH2 VIL fc fosc fFR Condition -- -- All inputs except VK VK All inputs -- R=4.7 kW, C=10 pF -- Min. 8 -40 3.8 3.8 0 -- -- -- Typ. -- -- -- -- -- -- 3.33 200 Max. 18 85 5.5 VDD 0.8 250 -- -- Unit V C V V V kHz MHz Hz
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta=-40 to +85C, VDD=8 to 18V) Parameter "H" Input Voltage "L" Input Voltage "H" Input Current (1) "H" Input Current (2) "L" Input Current (1) "L" Input Current (2) "H" Output Voltage (1) "H" Output Voltage (2) Symbol VIH VIL IIH1 IIH2 IIL1 IIL2 VOH1 VOH2 Condition All inputs except VD All inputs except VD All inputs except COL1-4 VIN=4.4 V COL1-4, VIN=3.8 V All inputs except COL1-4 VIN=0 V COL1-4, VIN=0 V SEG, GRID IOH1=-5 mA, VDD=9.5 V DATA I/O, VDD=9.5 V IOH2=-200 mA Output open SEG,GRID, VDD=9.5 V IOL1=500 mA IOL1=200 mA IOL1=2 mA DATA I/O, ROW1-3 VDD=9.5 V, IOL2=200 mA fosc=3.3 MHz, no load Min. 3.8 -- -5 -70 -5 -160 VDD-0.8 Max. -- 0.8 5 -5 5 -10 -- Unit V V mA mA mA mA V
4 4.5 -- -- -- -- --
-- -- 2 1 0.3 0.8 20
V V V V V V mA
"L" Output Voltage (1)
VOL1
"L" Output Voltage (2) Current Consumption
VOL2 IDD
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Semiconductor Switching Characteristics
MSC1215-XX
(Ta=-40 to +85C, VDD=8 to 18 V) Parameter Oscillation Frequency Clock Frequency Clock Pulse Width Data Set-up Time Data Hold Time CS Pulse Width CS Off Time CS Pulse Width CS Off Time CS Set-up Time CS-clock Time CS Hold Time Clock-CS Time DATA Output Delay CLCOK-DATA Out Time SEG & GRID Outputs Delay Time from CS Slew Rate (All Drivers) Symbol fosc fc tcw tDS tDH tCSW tCSL tRCSW tRCSL tCSS tCSH tPD tODS tR Condition -- -- -- -- -- Except reset mode Except reset mode Reset mode Reset mode -- -- -- CL=100 pF CL=100 pF t=20% to 80% or 80% to 20% of VDD -- Min. 2 -- 1.3 1 200 8 32 4 4 2 2 -- -- -- Max. 4.5 250 -- -- -- -- -- -- -- -- -- 1 8 5 Unit MHz kHz ms ms ns ms ms ms ms ms ms ms ms ms
Power on Timing
tPCS
300
--
ms
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Semiconductor Analog Dimming Characteristics
MSC1215-XX
(Ta=-40 to +85C, VDD=8 to 18V) Parameter D/A Ouput Voltage Error Reference Voltage Accuracy *1 Condition -- -- Min. -- -- Typ. -- -- Max. 3 6 Unit % %
*1 Reference voltage is 6.6 V typical. A/D Converter Characteristics
(Ta=-40 to +85C, VDD=8 to 18 V) Parameter A/D Conversion Accuracy Reference Voltage (VREF) Output Current Input Voltage Range Conversion Time/Channel Condition -- *2 -- -- fOSC=3.3MHz Min. -- 4.5 -- GND 384 Typ. -- 5 -- -- 543 Max. 1 5.5 4 VREF 896 Unit LSB V mA V ms
*2 When six loads of 10 kW are connected in parallel. Keyscan Characteristics
(Ta=-40 to +85C, VDD=8 to 18 V) Parameter Keyscan Cycle Time Keyscan Pulse Width Condition fOSC=3.3MHz fOSC=3.3MHz Min. 220 55 Typ. 312 78 Max. 512 128 Unit ms ms
PWM Conversion Characteristics
(Ta=-40 to +85C, VDD=8 to 18 V) Parameter PWM Input Frequency Rise/Fall Time PWM Pulse Width Input Duty Cycle "H" Input Threshold voltage "L" Input Threshold voltage Hysteresis Width Condition -- tr=10%AE90%, tf=90%AE10% t=50%AE50% VD pin VD pin VD pin VD pin Min. 112 100 125 1.65 0.26VDD 0.20VDD 0.02VDD Typ. 122 300 -- -- 0.28VDD 0.22VDD 0.06VDD Max. 132 800 -- 98.3 0.30VDD 0.24VDD 0.10VDD Unit Hz ms ms % V V V
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TIMING DIAGRAM
tCSW 3.8 V 0.8 V tCSS tcw CLOCK 3.8 V 0.8 V tDS tDH DATA I/O (INPUT) 3.8 V 0.8 V VALID VALID tDS tDH fc tcw tCSH tCSL
CS
Figure 1. DATA Input Timing
CS
3.8 V 0.8 V tCSS tCSH
CLOCK
3.8 V 0.8 V tPD tPD
DATA I/O (OUTPUT)
3.8 V 0.8 V
Figure 2. DATA Outpout Timing
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8V VDD tPCS tRCSW tRCSL
CS
3.8 V 0.8 V
Figure 3. Power-on-Reset Timing
tCSW CS 3.8 V 0.8 V tODS tR SEG1-17 GRID1, 2 80% 20% tODS tR
Figure 4. SEG and GRID Output Timing
1 Frame Cycle fFR 4096-bit times GRID1 16-bit times min GRID2 2032-bit times
6-bit times SEG1-17 2038-bit times 10-bit times
Figure 5. SEG-GRID output Timing (Daylight Mode) Note: 1. Timing shown for analog dimming with a duty cycle of 2032/2048 at VK="L". 2. 1-bit time=TOSC (=4/fOSC)=1.2 s typical.
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1 Frame Cycle fFR 4096-bit times GRID1
2048-bit times GRID2 208-bit times max.
SEG1-17
Figure 6. SEG-GRID output Timing (Dark Mode) Note: 1. Timing shown for analog dimming with a duty cycle of 208/2048 at VK="H". 2. 1-bit time=TOSC (=4/fOSC)=1.2 s typical.
90% VD (PWM Input) 50% 10% tr tPW T tf
Figure 7. PWM Waveform
Keyscan Cycle Time ROW1 Keyscan Pulse Width ROW2
ROW3
Figure 8. Keyscan Timing Note: 1. Key scanning from ROW1 to ROW3 is started when any key is pushed down or released. Scanning will stop when CS turns to "L" from "H", after 2 times of CS pulses and the transfer of display data.
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MSC1215-XX
Push Keyscan Keyscan Stop
CS Display Data Output
Figure 9. Keyscan Stop Timing
FUNCTIONAL DESCRIPTION
Pin Functional Description * VDD Power supply input pin Connected to a 12V power supply * GND Ground Pin This pin is 0V level. * CLOCK Serial clock input pin * CS Chip select input pin When "H" is input to this pin, interfacing with a MCU is available through the CLOCK and the DATA pins. Therefore, 2 signal lines of the CLOCK and the DATA can be shared with other peripherals. * DATA I/O (Input-output) Serial data input-output pin This pin inputs display data and outputs keyscan and A/D conversion data. * VK Daylight/dark mode selection input pin When "H" is input, the dark mode is selected and an output duty cycle is determined by analog or PWM data input into the VD pin. When "L" is input, the daylight mode is selected and the output duty cycle becomes about 100%. * VD Analog/PWM dimming data input pin Analog/PWM dimming mode selection will be done by an internal detection circuit automatically. * VREF Reference voltage output pin for the A/D converter 12/22
Semiconductor
MSC1215-XX
* CH1-6 Analog voltage input pin for the A/D converter * COL1-4 Key matrix input pins These pins are active "Low" and pulled up to "H" through built-in resistors except when "L" is input by a pushed down key. * ROW1-3 Key matrix scanning output Normally ROW1-3 output "L", by detecting the key switch to be pushed down or released, a key scan starts, sending CS pulses two times and VF data, after above turning the CS pin to "L" from "H". After scan stops, all the ROW outputs turn to "L". * OSC0, 1 RC oscillation input pins A resistor and a capacitor are connected to these pins. (See figure below)
OSC1 R OSC0 C
* SEG1-17 Segment output pins * GRID1, 2 Grid output pins Output an inverted signal of a grid signal. These pins are connected to inputs of external drivers (such as a PNP transistor).
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Semiconductor Functional Flowchart
MSC1215-XX
POWER-ON (Power-on Reset)
*1
Display Data Input Mode *2 2CS Pulses CS="H" Dispaly Data Input (34 bits) Test Data Input (3 bits) Input Total (37 bits)
CS="L"
Keyscan Data Output Mode
CS="H"
Keyscan Data Output (12 bits)
CS="L"
A/D Data Output Mode
CS="H"
A/D Data Output (36 Bit)
CS="L"
Note: 1. When power supply turns on, the internal circuits are initialized as follows by the built-in power-on reset circuit. * Display data input mode is selected * All segment outputs are in OFF state ("L") * All internal registers and latches are set to "0" level 2. The status of the internal circuit after serial 2 CS pulses were applied, are as follows. * Display data input mode is selected * The other status are the same as before the serial 2CS pulses were applied.
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Semiconductor Display Data Input
MSC1215-XX
Data input is available only when "H" is applied to the "CS" pin. Input data is shifted into shift registers through the "DATA I/O" pin at the rising edge of the clock. The data is automatically loaded to latches at the falling edge of "CS" signal. [Data Format]
Bit Data 37 34 36 33 35 32 Display Data 6 3 5 2 4 1 3 T3 2 T2 Test Data *1 1 T1 First in
Note: Three bits (T1 to T3) for the test data are used for shipping inspection. For the normal operation mode, all these bits should be set to "0" level. Keyscan Data Output Data output is available only when "H" is applied to the "CS" pin. When keyscan data output mode is selected, "DATA I/O" pin is changed to an output mode. Then, 12 bits of keyscan data come out from "DATA I/O" pin synchronizing with the rising edge of the clock. This output mode is changed to A/D data output mode at the falling edge of the CS input signal. To select directly the display input mode from this output mode, serial 2CS pulses should be input to the CS pin. [Data Format]
Bit Data 12 11 10 9 8 7 6 5 4 3 2 1 First out
S34 S33 S32 S31 S24 S23 S22 S21 S14 S13 S12 S11 *2
Note: Symbols of the keyscan data are as follows.
SRC COL Number (COL1-4) ROW Number (ROW1-3)
A/D Data Output A/D data output is available only when "H" is input to the CS pin. When the A/D data output mode is selected, DATA I/O pin is changed to an output mode. Then 36 bits of A/D data come out from DATA I/O pin synchronizing with the rising edge of the shift clock. This output mode is changed to the display input mode at the falling edge of the CS input signal. [Data Format]
Bit Data 36-31 MSB-LSB CH6 30-25 MSB-LSB CH5 24-19 MSB-LSB CH4 18-13 MSB-LSB CH3 12-7 MSB-LSB CH2 6-1 MSB-LSB CH1 First out
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Semiconductor Keyscan
MSC1215-XX
To keep a scanning noise to a minimum, a scanning of the key switch starts only when a key is pushed down or released. The scanning stops when CS input turns to "L" from "H" after sending CS pulses two times and display data. [Key Matrix of COL Input and ROW Output]
ROW1 S11 S12 S13 S14 ROW2 S21 S22 S23 S24 ROW3 S31 S32 S33 S34 COL1 COL2 COL3 COL4
=
A/D Conversion The IC has a built-in 6-ch 6-bit A/D converter. As shown in the circuit below, the VREF output pin is connected to a variable resistor forming a voltage divider and the divided analog voltage is used to input into the CH1 to CH6 pins. [Circuit Example]
VREF Variable Resistor CH1
PWM Dimming Lamp PWM signal is input to the VD pin and converted to VF display PWM signal by the PWM conversion circuit. The conversion table is mark-programmable. Note: The duty cycle of the lamp PWM signal is measured with a reference point of the threshold voltage of the VD input pin. The threshold voltage changes due to process parameter deviation. Therefore, the PWM conversion error increases as the rise/fall time of the lamp PWM increases.
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Semiconductor Analog Dimming
MSC1215-XX
The PWM duty cycle is controlled by analog voltage which is the output of the brightness control volume on a dashboard. The dimming curve is mask-programmable with the following limitations; 1. Maximum duty cycle is 12.5%.
12.5% Max 12.5% 100% (DUTY) 512kHz DUTY CYCLE STEP
2. Number of pulse stops is max. 52. 3. Input Voltage to "VD" The input voltage to "VD" needs to use a voltage divider as shown below.
2R VD-IN R VD
Note: The maximum voltage to the VD is 5V. 4. Maximum Threshold Voltage The maximum threshold voltage is 5.0V. 5. Minimum & Maximum VDIM Input Voltage The minimum threshold voltage step is 20mV. Only for the first step, the threshold voltage can be any value between 20mV and 3V.
min 20mV max 3V
0
1
2
3
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Semiconductor PWM Conversion Table
LAMP PWM VFD PWM LAMP PWM VFD PWM STEP No. DUTY CYCLE DUTY CYCLE STEP No. DUTY CYCLE DUTY CYCLE 100.00% 12.50% 58.75% 0 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 98.75% 97.50% 96.25% 95.00% 93.75% 92.50% 91.25% 90.00% 88.75% 87.50% 86.25% 85.00% 83.75% 82.50% 81.25% 80.00% 78.75% 77.50% 76.25% 75.00% 73.75% 72.50% 71.25% 70.00% 68.75% 67.50% 66.25% 65.00% 63.75% 62.50% 61.25% 60.00% 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 57.50% 56.25% 55.00% 53.75% 52.50% 51.25% 50.00% 48.75% 47.50% 46.25% 45.00% 43.75% 42.50% 41.25% 40.00% 38.75% 37.50% 36.25% 35.00% 33.75% 32.50% 31.25% 30.00% 28.75% 27.50% 26.25% 25.00% 23.75% 22.50% 21.25% 20.00%
MSC1215-XX
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Semiconductor Dimming Voltage-Pulse width Correspondence Table
MSC1215-XX
VDI Threshold dimming voltage vs. PWM duty cycle (Typical Value) 12.5% PWM maximum table
Pulse Step Number 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 PWM Duty Cycle Pulse Count 256/2048 240/2048 224/2048 208/2048 192/2048 184/2048 176/2048 168/2048 160/2048 152/2048 144/2048 136/2048 128/2048 120/2048 112/2048 104/2048 96/2048 92/2048 88/2048 84/2048 80/2048 76/2048 72/2048 68/2048 64/2048 60/2048 % 12.5 11.7 10.9 10.2 9.38 8.98 8.59 8.20 7.81 7.42 7.03 6.64 6.25 5.86 5.47 5.08 4.69 4.49 4.30 4.10 3.91 3.71 3.52 3.32 3.13 2.93 Threshold Pulse Step PWM Duty Cycle Voltage Number Pulse Count % 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 56/2048 52/2048 48/2048 46/2048 44/2048 42/2048 40/2048 38/2048 36/2048 34/2048 32/2048 30/2048 28/2048 26/2048 24/2048 23/2048 22/2048 21/2048 20/2048 19/2048 18/2048 17/2048 16/2048 15/2048 14/2048 13/2048 2.73 2.54 2.34 2.25 2.15 2.05 1.95 1.86 1.76 1.66 1.56 1.46 1.37 1.27 1.17 1.12 1.07 1.03 0.98 0.93 0.88 0.83 0.78 0.73 0.68 0.63 0.000 (@VDD=2.8 V) Threshold Voltage
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APPLICATION CIRCUITS
Dimming Mode
1 12 V VDD GND DATAI/O CLOCK CS VREF CH1 12 V Small Lamp Switch CH6
2 ROW
3
1
2
3 COL
4 12 V
Microcontroller
GRID1
12 V MSC1215-XX GRID2
VK Dashboard Lamp Lamp PWM Signal VD SEG1 OSC1 OSC0 SEG17
1/2 Duty VF Display Tube
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Semiconductor Analog Dimming Mode
MSC1215-XX
1 12 V
Microcontroller
2 ROW
3
1
2
3 COL
4 12 V
VDD GND DATAI/O CLOCK CS VREF CH1 12 V 12 V MSC1215-XX GRID2 CH6 GRID1
Small Lamp Switch
VK Brightness Control Resistor Dashboard Lamp OSC1 VD SEG1 OSC0 SEG17
1/2 Duty VF Display Tube
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Semiconductor
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PACKAGE DIMENSIONS
(Unit : mm)
DIP42-P-600-2.54
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 6.20 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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